1. Technical Field
Embodiments of the invention relate to a method of fabricating a semiconductor device. More particularly, embodiments of the invention relate to a method of fabricating a semiconductor device using selective epitaxial growth.
This application claims the benefit of Korean Patent Application No. 10-2005-0060247, filed Jul. 5, 2005, the disclosure of which is hereby incorporated by reference in its entirety.
2. Discussion of Related Art
Contemporary semiconductor devices are fabricated on a substrate through the application of a complex sequence of processes. Among these fabrication processes, epitaxial processes are increasingly used to form various elements, such as trench type isolation regions, plug contacts connecting source and drain regions, etc. In one particular application, one or more epitaxial processes may be used during the fabrication of SRAM devices having a stacked structure (e.g., two or more transistors stacked along a common vertical axis).
The term “epitaxial” generally refers to any process in which a material layer transition occurs along one or more crystalline axes. As is well known in the art, certain materials, including semiconductor and semi-insulating materials, may be used in conjunction with an epitaxial process. In one common application, an epitaxial process is used to grow a single crystal layer having defined “orientation” (e.g., an atomic lattice geometry) on a semiconductor substrate. The semiconductor substrate, or a material layer formed on the substrate imparts the defined orientation to a material layer grown by the epitaxial process. The growth of single crystal silicon on a silicon semiconductor substrate is a common object of conventional epitaxial processes.
Epitaxial processes have many benefits including the growth of very pure (e.g., contamination and defect free) material layers. In many instances, such material layers may also be grown at temperatures much lower than competing fabrication processes.
Epitaxial processes may be generally classified into three types in relation to their principle method of deposition; vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), and molecular beam epitaxy (MBE). VPE is characterized by the use of a process gas to grow a material layer. LPE is characterized by the use of a saturated solution or molten source to grow a material layer. MBE is characterized by the use evaporated materials in an ultra-high vacuum state (e.g., a vacuum ranging from 9 to 10 Torr) and application of an energy beam to grow a material layer.
Selective epitaxial growth (SEG) is one class of epitaxial processes well adapted to the growth of a single crystal layer on only selected portion(s) of a semiconductor substrate. SEG typically involves segregation of a substrate surface, potentially having intervening structures formed thereon, into regions to be reacted (i.e., wherein the desired material layer will be grown using SEG) and regions not to be reacted. For example, in a region where an epitaxial layer is to be grown, the surface of the constituent semiconductor substrate may be selectively exposed by removing an intervening protective layer, such as silicon oxide using conventional photo-lithography and etching processes. The exposed portion of the substrate surface from which the desired material is grown and from which the desired material layer receives its crystalline orientation is referred to as a “seed” layer (or alternatively seed material, etc.). For example, U.S. Pat. No. 5,843,826, the subject matter of which is incorporated by reference, discloses an exemplary SEG process adapted to solve problems associated with etch margin as it relates to contact holes when source and drain regions are formed at a shallow depth.
In FIGS. 1A to 1C, a conventional method of fabricating a semiconductor device having a single stack layer using SEG is shown.
First, referring to FIG. 1A, a semiconductor substrate 10, for example of P type, comprises active and field regions defined by a trench isolation layer 12, and a gate region 14 having sidewall spacers 16. Penta-valent dopant ions have been selectively implanted into regions of semiconductor substrate 10 peripheral to gate region 14 to form doped diffusion regions serving as source and drain regions.
Subsequently, a buffer layer 18 (e.g., silicon nitride) and an oxide layer 20 (e.g., a high temperature oxide) are sequentially deposited on semiconductor substrate 10 to thicknesses of about 200 Å and 600 Å respectively to form an interlayer insulating layer. A seed window 22 exposing a source or drain region in semiconductor 10 is formed using a conventional photo-lithography process. The seed portion of semiconductor substrate 10 exposed through seed window 22 is subjected to an SEG process at a pressure ranging from between about 5 to 200 Torr at a temperature ranging from between about 700 to 750° C. As a result, a SEG layer 24 of single crystal silicon material similar to semiconductor substrate 10 is epitaxially grown in seed window 22.
Referring now to FIG. 1B, in order to continue the particular (and exemplary) SEG process associated with SEG layer 24, an amorphous silicon layer is deposited and patterned on semiconductor substrate 10 to contact SEG layer 24 to a thickness of about 250 Å. Once formed and patterned, the amorphous silicon layer acts as a channel silicon pattern 26. Channel silicon pattern 26 is a region adapted to receive a gate region associated with an upper transistor ultimately stacked on top of a lower transistor associated with gate region 14.
Referring to FIG. 1C, an annealing process 28 is performed on semiconductor substrate 10. In relation to the illustrated example, annealing process 28 is carried out at a temperature of about 600° C. for about 12 hours (e.g., an annealing interval). As a result of annealing process 28, SEG layer 24 acts as a seed for the growth of single crystal silicon (26a) from the patterned amorphous silicon layer forming channel silicon pattern 26. Single crystal silicon layer 26a is materially similar to SEG layer 24.
Subsequently, single crystal silicon layer 26a may be formed into a gate region having sidewall spacers as well as associated dopant diffusion regions functioning as source and drain regions in order to form the upper transistor.
The method illustrated in FIGS. 1A to 1C is drawn to an example of fabricating a SRAM having a single stack layer structure in view of contemporary design rules. In one aspect, this conventional method is advantageous in that it is capable of forming a channel silicon pattern on a desired region by forming an amorphous silicon layer into a single crystal layer using SEG layer 24 formed through seed window 22.
The constituent annealing process performed on the amorphous silicon layer is a heat treatment process adapted to rearrange silicon atoms in the amorphous silicon layer and thereby repair defects caused by ion implantation and other processes. In effect, the applied heat treatment re-arranges the silicon atoms to yield a silicon layer having an essentially uniform material lattice structure formed with a consistent orientation, or a “single crystal silicon layer.”
One measure of lattice structure uniformity is the distance between neighboring atoms along a given orientation. Exemplary distances are shown in Table 1 for various material layer types (e.g., poly-types) and standard crystalline orientations.
TABLE 1BodyFaceCenteredCenteredSimple CubicCubicCubicDiamondStructureStructureStructureStructure<100>aaaa<110>{square root over (2)}a{square root over (2)}a  a      2    a      2   <111>{square root over (3)}a            3        ⁢    a    2{square root over (3)}a                              3                ⁢        a            4        &    ⁢            3      ⁢              3            ⁢      a        4  
As shown in Table 1, the distance between the neighboring atoms varies according to crystalline orientation, as defined by the Miller index. For example, in the simple cubic structure of the silicon, the distance between the neighboring atoms is “a” for crystal orientation <100>, while the distance between the neighboring atoms is “√{square root over (3)}a” for crystal orientation <111>. Further, in a diamond structure of silicon, the distance between the neighboring atoms is “a” for crystal orientation <100>, while the distance between the neighboring atoms is
  Ó  ⁢                    3            ⁢      a        4    ⁢  Ô  ⁢                    ⁢                  ⁢  and  ⁢          ⁢  Ó  ⁢            3      ⁢              3            ⁢      a        4    ⁢  Ôfor crystal orientation <111>.
In a truly “single crystal silicon” material, the respective distances between neighboring atoms will be constant regardless of specific poly-type. However, in the amorphous silicon, the distance between the neighboring atoms is not constant due to its inherently irregular arrangement of silicon atoms. In order to convert the amorphous silicon into the single crystal silicon, the conventional annealing process is performed.
The process of converting amorphous silicon into single crystal silicon using an annealing process is further illustrated in FIGS. 2A to 2C.
Referring to FIG. 2A, an amorphous silicon layer 52 is formed on a single crystal silicon layer 50. In order to convert amorphous silicon layer 52 into single crystal silicon layer 50, an annealing process using single crystal silicon layer 50 as a seed is carried out. In one embodiment, the annealing process is carried out at a temperature of about 600° C. Under the influence of the annealing process, amorphous silicon layer 52 is changed into a layer of polycrystalline silicon 56 comprising a plurality of large grain boundaries 54, as shown in FIG. 2B.
As the annealing process continues, the bonding force between the silicon atoms is weakened. As a result, amorphous silicon layer is changed into a single crystal silicon layer 58 having similar material properties as the seed-single crystal silicon layer 50. See, FIG. 2C.
As noted, the exemplary, conventional annealing process is performed at a temperature of about 600° C. This annealing temperature of 600° C. is relatively low, so that a mean free path of the silicon atom is short. Therefore, if the annealing process is not adequately performed, the amorphous silicon will not be completely converted into the single crystal silicon, and thus the amorphous silicon will coexist with the crystalline silicon (e.g., a resulting mixture of poly-crystal and single-crystal materials).
In order to avoid this result, it is typically preferable to maintain the annealing process for a sufficiently long time. Thus, the conventional SEG process described with reference to FIGS. 1A to 1C comprises an annealing process that applies a temperature of about 600° C. for about 12 hours. This approach to annealing has been shown to yield excellent single crystal silicon from amorphous silicon. However, the 12 hour duration of the conventional annealing process poses a significant temporal bottleneck to the efficient fabrication of semiconductor devices. Yet, shorter durations run the risk of yielding poor quality single crystal silicon.